1. Field of the Invention
The present invention generally relates to data transfer systems, and particularly relates to a DMA transfer system.
2. Description of the Related Art
A DMA (Direct Memory Access) transfer system makes it possible to perform high-speed data transfer by transferring data directly from the transfer source to the transfer destination without using a CPU. FIG. 1 is a drawing showing an example of the configuration of a related-art DMA transfer system.
A DMA transfer system 10 shown in FIG. 1 includes a CPU 11, a DMA controller (DMAC) 12, a memory 13, a memory 14, and a system bus 15. The CPU 11, the DMA controller 12, the memory 13, and the memory 14 are connected to each other via a system bus 15.
The CPU 11 specifies a transfer source address, a transfer destination address, a transfer data size, the number of transfers, etc., for DMA, thereby making DMA transfer settings to the DMA controller 12. In response, the DMA controller 12 performs the specified DMA transfer. For example, the DMA controller 12 reads data with the size specified by the transfer data size from the transfer source address in the memory 13, and transfers the data to the transfer destination address in the memory 14. The DMA controller 12 performs this data transfer as many times as specified while successively incrementing or decrementing the transfer source address and the transfer destination address. With this provision, the CPU 11 can attend to other processing while the DMA transfer is performed.
The DMA controller 12 includes a channel arbiter 21, one or more channels 22, and a FIFO 23. The channels 22 correspond to respective DMA transfer processes that are performed independently of each other. If n channels are provided, n DMA transfer processes, which are independent of each other, can be performed. One channel 22 includes a DMA control circuit 24 and a channel register 25. DMA transfer settings by the CPU 11 as described above is performed with respect to the channel register 25 of each of the channels 22.
The channel register 25 includes registers such as a transfer request register, a transfer mode register, a transfer width register, a transfer count register, a transfer source address register, a transfer destination address register, and an option register. The transfer request register stores a setting indicative of the presence/absence of a transfer request. The transfer mode register stores a setting indicative of the type of transfer such as a single transfer or a burst transfer. The transfer width register stores a setting indicative of the width of transfer such as a byte/half word/word. The transfer count register stores a setting indicative of the number of data transfers performed by use of the above-noted transfer mode and transfer width. The transfer source address register stores a setting indicative of the address in memory from which data is to be read. The transfer destination address register stores a setting indicative of the address in memory to which data is to be written. The option register stores settings relating to transfer options that are not necessarily required for DMA transfer. Such settings includes a temporal pause, a forced suspension, the reloading of an address or the number of transfers upon the completion of transfer, the selection of the presence/absence of an interruption signal, etc. The CPU 11 makes these settings via the system bus 15.
The channel arbiter 21 ceaselessly checks the transfer request register of each of the channels 22. When there is a transfer request, a channel 22 that is going to perform the DMA transfer is selected according to a predetermined priority system from the plurality of channels 22 that are requesting transfer. The channel arbiter 21 notifies the selected channel 22 that it has been selected. When the channel 22 notified of its selection withdraws a transfer request after performing its transfer process, the channel arbiter 21 selects a channel 22 that is going to perform a next DMA transfer among the plurality of channels 22 that are requesting transfer.
The predetermined priority system that is used by the channel arbiter 21 to select a channel 22 to perform a DMA transfer may include the “fixed priority system” and the “rotating priority system”. The fixed priority system uses fixed priority levels assigned to the channels, so that the channel having the highest priority is always selected for DMA transfer. This priority system is effective when it is clear as to what priority levels should be given to respective channels (transfer paths). In the rotating priority system, the priority levels rotate by using as a reference the channel that has performed the latest DMA transfer. This priority system is effective when all the transfers need to be performed in parallel without giving priority to a particular channel.
When the channel arbiter 21 selects a channel 22 and notifies of its selection, the DMA control circuit 24 of the channel 22 notified of its selection becomes the bus master of the system bus 15, and performs DMA transfer. Namely, the DMA control circuit 24 accesses the transfer source address (e.g., address in the memory 13) indicated by the transfer source address register via the system bus 15, thereby reading data with the data size specified by the transfer width register to the system bus 15. The read data is temporarily stored in the FIFO 23. Further, the DMA control circuit 24 writes the read data stored in the FIFO 23 to the transfer destination address (e.g., address in the memory 14) specified by the transfer destination address register by using the intervening system bus 15.
Upon the completion of the DMA transfer, the channel 22 having completed the DMA transfer withdraws the transfer request in its transfer request register, resulting in the DMA control circuit 24 asserting an interruption signal indicative of the completion of transfer.
In recent years, the number of transfers that need to be performed simultaneously has been on the increase due to an increase in the sophistication of various processes (e.g., multimedia processes) performed in systems. This leads to a demand to increase the number of channels implemented in a DMA controller. However, an increase in the number of channels implemented in a DMA controller leads to an increase in circuit size. In technical fields in which chip size and power consumption are important issues, such as in the case of LSI for mobile terminals, an increase in circuit size is extremely costly.
On the other hand, if the number of channels implemented in a DMA controller is small in comparison with the number of transfer paths simultaneously requested, the overall performance of the system may drop. In such a case, a configuration in which the CPU controls DMA transfers by arbitrating the transfer requests results in an increase in the load on the CPU. In order to reduce the load on the CPU, the number of channels in the DMA controller may be increased. Since the DMA controller is designed as hardware, however, it is difficult to increase/decrease only the number of channels. In consideration of this, the system may be configured such that a plurality of DMA controllers 12-1 through 12-3 are implemented as shown in FIG. 2. In this configuration, however, the plurality of DMA controllers 12-1 through 12-3 compete against each other in an attempt to capture the system bus 15 each time a given transfer comes to an end. Drop in performance is thus unavoidable. Also, the circuit size increases in accordance with the number of DMA controllers that are implemented.
Moreover, since transfer functions required of a DMA controller differ from system to system, the provision of a DMA controller only having simple transfer functions in each system cannot guarantee sufficient transfer performance. Because of this, it is preferable to design a DMA controller having transfer functions specialized for a particular system when the performance of a system is given emphasis. When a DMA controller designed in such manner is used in another system, however, the specialized transfer functions may not be made use of properly. This means that there is an excess circuitry. Further, if a DMA controller is designed such as to be optimized for each system, the process steps such as a design step, a development step, and a test step are required for each system. This is costly.    [Patent Document 1] Japanese Patent Application Publication No. 2003-256356    [Patent Document 2] Japanese Patent Application Publication No. 2003-242098
Accordingly, there is a need for a DMA transfer system that can increase the number of channels without causing an increase in circuit size, and that can provide sophisticated functions without being functionally specialized for a particular system.